The field of integrated circuit interconnection and packaging is one of the most rapidly evolving technologies associated with semiconductor manufacturing. As demand for devices that are smaller and more powerful continues to increase, pressure is put on manufacturers to develop better and more efficient ways to assemble and package IC products. Much work in this field has been focused on peripheral memory-chip packages with wire bond chip-to-package interconnects, and mounting and connecting such devices onto PCB modules in such a way that storage capacity and function speed of the memory module is increased while vertical height and footprint of mounted devices is kept to a minimum. Such memory devices often utilize devices with Thin Small Outline Package (TSOP) pin configurations, utilizing various well known chip-flipping and stacking technologies. Recent solutions utilizing chip-size package (CSP) devices have incorporated surface mount area solder ball technology such as Ball Grid Array (BGA) and other wafer-level packaging schemes known to the inventor. Such solder ball interconnection methods eliminate the need for outer-edge pad arrangements such as those used for typical TSOP memory chips, for example, and strengthen and protect the connection leads from damage during handling which can hinder or eliminate signal propagation. Also, connection leads can be fanned out in an area array in much greater numbers, increasing available I/O leads, utilizing an otherwise unused area under the chip. Many other clear and important advantages over other mainstream interconnect technologies such as Fine-Pitch-Technology (FTP), and Pin-Grid-Array (PGA), driving much of the focus in development in such CSP area-array interconnect schemes.
In enhanced CSP technology such as described above, wafers or substrates are typically protected with a non-conductive material such as a polyamide layer, for example. The die pads are exposed through the protective layer by means of chemical etching, or by other known methods. The protective layer is intended to protect the circuits from contaminants and damage. One problem with prior-art protective wafer-level coatings such as described is that such coatings are ultra-thin and do not offer much mechanical protection to the die pads themselves, nor to the connection points between solder balls in the die pads.
There are several enhancements known to the inventor for techniques utilized in wafer-level packaging for CSP devices of BGA technology. In one of these enhancements, a process involving application of an additional protective polymer coating is applied at wafer level to the connection side of the wafer. The process is taught in the patent application Ser. No. 09/609,626, entitled “Method and Apparatus for Applying a Protective Over-coating to a Ball-Grid-Array (BGA) Structure”, which is referenced above as a priority document.
A method and apparatus in the above-referenced patent application comprises an upper plate having at least one injection port forming the upper chamber wall, and a lower plate having at least one vacuum port forming the lower chamber wall of the vacuum-application and coating apparatus when assembled. A compliant layer of material is provided on the chamber-side surface of the upper plate and a sealing mechanism for enabling a vacuum seal is also provided. At least one assembly to be coated is placed on the chamber surface of the lower plate during assembly of the vacuum-application and coating apparatus, which forms a vacuum chamber. The ball-grid-array assemblies held in the chamber are protected from receiving any coating on the upper portions of connected solder balls during processing by virtue of intimate contact between the solder balls and the compliant layer of material.
The above-described process provides protection for die-pads and solder connections of BGA-type ICs. The inventor also has knowledge of methods for building or extending contact surfaces of a BGA assembly to the surface of the package through protective coatings and then back grinding the assembly in order to reduce weight and thermal mass of the chip package. One such method is photoresist polymerization where solder columns are formed prior to application of the photosensitive polymer coating.
The process of chip stacking, as described earlier for TSOP memory chips, is an emerging technology involving integration of two, or possibly more, chip devices together on a single board. Chip stacking can greatly increase the memory capacity of a memory module, for example, without unduly increasing the footprint of the device. Types of stacked chip packages include Chip Scale Packages (CSP), True Chip Size Packages (TCSP) and True Die Size Packages (TDSP). TCSP and TDSP packages include devices such as Dynamic Random Access Memory (DRAM), flash memory as well as many others, typically employed in products such as hand-held computers and other small electronic devices for communications, and elsewhere where density and low profile is of importance. Assembling CSP devices using BGA technology already allows for a smaller form factor for ICs than is available in competing technologies such as wire bond methods, and by utilizing chip stacking techniques in this technology substantial increases in price-performance and capacity and reliability may be realized. The contributions described above with respect to mentioned processes known to the inventor provide considerable strengthening and improved signal propagation than do known prior-art methods.
In general manufacturing of memory-type devices, it is desirable to increase memory capacity of the device while minimizing the bulk and footprint of the memory module of the host device. Modules built with wire bond techniques are very difficult to economically increase capacity in such a manner. It is known that CSP/BGA devices provide smaller form factor than other mainstream technologies. It has occurred to the inventors that it would be desirable to stack chips on a single board so as to multiply the memory power available to the resulting module of equivalent prior-art modules. However, a method and apparatus must be conceived in order to provide economical assembly and packaging while keeping the overall size profile of the memory packages small. It is to this goal that the methods and apparatus of the present invention more particularly pertain.
What is therefore clearly needed is a method and apparatus for enabling a chip integration technique to be applied to device boards wherein memory, and in some cases, other functional ICs may be integrated and added to a device board without requiring larger X, Y (footprint) or, in many cases Z dimension increases in existing form-factors. Such a method and apparatus would allow devices to be manufactured or retrofitted with a multiple of added memory devices without utilizing more physical space.